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semiconductor group 1 semiconductor group 6.97 ? 4 194 304 words by 16-bit organization ? 0 to 70 c operating temperature ? fast page mode operation ? performance: ? single + 3.3 v ( 0.3v) power supply ? low power dissipation: 7.2 mw standby (ttl) 3.24 mw standby (mos) 720 m w standby for l-version ? read, write, read-modify-write, cas -before-ras refresh (cbr), ras -only ref resh, hidden refresh and self refresh (l-version only) ? 2 cas / 1 we byte control ? 8192 refresh cycles /128 ms , 13 r/ 9c addresses (hyb 3164160at) 4096 refresh cycles / 64 ms , 12 r/ 10c addresses (hyb 3165160at) 2048 refresh cycles / 32 ms , 11 r/ 11c addresses (hyb 3166160at) ? 256 msec refresh period for l-versions ? plastic package: p-tsopii-50 400 mil -40 -50 -60 t rac ras access time 40 50 60 ns t cac cas access time 10 13 15 ns t aa access time from address 20 25 30 ns t rc read/write cycle time 75 90 110 ns t pc fast page mode cycle time 30 35 40 ns -40 -50 -60 hyb3166160at(l) 900 558 396 mw hyb3165160at(l) 756 468 324 mw hyb3164160at(l) 612 378 270 mw 4m x 16-bit dynamic ram advanced information hyb 3164160at(l) -40/-50/-60 hyb 3165160at(l) -40/-50/-60 hyb 3166160at(l) -40/-50/-60 ( 8k, 4k & 2k refresh)
semiconductor group 2 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram this device is a 64 mbit dynamic ram organized 4 194 304 by 16 bits. the device is fabricated on an advanced second generation 64mbit 0,35 m m-cmos silicon gate process technology. the circuit and process design allow this device to achieve high performance and low power dissipation. this dram operates with a single 3.3 +/-0.3v power s upply and interfaces with either lvttl or lvcmos levels. multiplexed address inputs permit the hyb 3164(5)160at to be packaged in a 400 mil wide tsop-50 package. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. the hyb3164(5/6)160atl parts (l-version) have a very low power ?sleep mode supported by self refresh. ordering information type ordering code package descriptions 8k-refresh versions: hyb 3164160at-40 p-tsopii-50 400 mil dram (access time 40 ns) hyb 3164160at-50 p-tsopii-50 400 mil dram (access time 50 ns) hyb 3164160at-60 p-tsopii-50 400 mil dram (access time 60 ns) hyb 3164160atl-50 p-tsopii-50 400 mil dram (access time 50 ns) hyb 3164160atl-60 p-tsopii-50 400 mil dram (access time 60 ns) 4k-refresh versions: hyb 3165160at-40 p-tsopii-50 400 mil dram (access time 40 ns) hyb 3165160at-50 p-tsopii-50 400 mil dram (access time 50 ns) hyb 3165160at-60 p-tsopii-50 400 mil dram (access time 60 ns) hyb 3165160atl-50 p-tsopii-50 400 mil dram (access time 50 ns) hyb 3165160atl-60 p-tsopii-50 400 mil dram (access time 60 ns) 2k-refresh versions: hyb 3166160at-40 p-tsopii-50 400 mil dram (access time 40 ns) hyb 3166160at-50 p-tsopii-50 400 mil dram (access time 50 ns) hyb 3166160at-60 p-tsopii-50 400 mil dram (access time 60 ns) hyb 3166160atl-50 p-tsopii-50 400 mil dram (access time 50 ns) hyb 3166160atl-60 p-tsopii-50 400 mil dram (access time 60 ns)
semiconductor group 3 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram pin names a0-a12 address inputs for 8k-refresh version hyb 3164160at(l) a0-a11 address inputs for 4k-refresh version hyb 3165160at(l) a0-a10 address inputs for 2k-refresh version hyb 3166160at(l) ras row address strobe oe output enable i/o1-i/o16 data input/output ucas ,lcas column address strobe we read/write input vcc power supply ( + 3.3v) vss ground * pin 33 is a12 for hyb 3164160at(l) and n.c. for hyb 3165(6)160at(l) p-tsopii-50 (400 mil) ** pin 32 is a11 for hyb 3164(5)160at(l) and n.c. for hyb 3166160at(l) o vcc i/o1 i/o2 i/o3 i/o4 vcc i/o5 i/o6 i/o7 i/o8 n.c. vcc we ras n.c. n.c. n.c. n.c. a0 a1 a2 a3 a4 a5 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss i/o16 i/o15 i/o14 i/o13 vss i/o12 i/o11 i/o10 i/o9 n.c. lcas ucas oe n.c. n.c. a12/n.c. * a11/n.c.** a10 a9 a8 a7 a6 vss . vss . 27 26 pin configuration
semiconductor group 4 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram truth table function ras lcas ucas we oe row add col add i/o1- i/o16 standby h h - x h - x x x x x high impedance read:word l l h h l row col data out read:lower byte l l h h l row col lower byte:data out upper-byte:high-z read:upper byte l h l h l row col lower byte:high-z upper byte:data out write:word (early-write) l l l l x row col data in write:lower byte (early-write) l l h l x row col lower byte:data out upper-byte:high-z write:upper byte (early write) l h l l x row col lower byte:high-z upper byte:data out read-modify- write l l l h - l l - h row col data out, data in fast page mode read (word) 1st cycle l h - l h - l h l row col data out fast page mode read (word) 2nd cycle l h - l h - l h l n/a col data out fast page mode early writ e(word) 1st cycle l h - l h - l l x row col data in fast page mode early writ e(word) 2nd cycle l h - l h - l l x n/a col data in fast page mode rmw 1st cycle l h - l h - l h - l l - h row col data out, data in fast page mode rmw 2st cycle l h - l h - l h - l l - h n/a col data out, data in ras only refresh l h h x x row n/a high impedance cas-before-ras refresh h - l l l h x x n/a high impedance test mode entry h - l l l l x x n/a high impedance hidden refresh (read) l-h- l l l h l row col data out hidden refresh (write) l-h- l l l l x row col data in
semiconductor group 5 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram block diagram for hyb 3164160at(l) no. 2 clock generator column address buffer(9) refresh controller refresh counter (13) address buffers(13) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 8192x512x16 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we ucas 8192 512 x16 . ras 9 13 16 i/o1 i /o2 oe 13 13 a10 a11 16 16 9 i /o16 lcas . a12
semiconductor group 6 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram block diagram for hyb 3165160at(l) no. 2 clock generator column address buffer(10) refresh controller refresh counter (12) address buffers(12) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 4096x1024x16 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we ucas 4096 1024 x16 . ras 10 12 16 i/o1 i /o2 oe 12 12 a10 a11 16 16 10 i /o16 lcas .
semiconductor group 7 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram block diagram for hyb 3166160at(l) no. 2 clock generator column address buffer(11) refresh controller refresh counter (11) address buffers(11) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 2048x2048x16 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we ucas 2048 2048 x16 . ras 11 11 16 i/o1 i /o2 oe 11 11 a10 16 16 11 i /o16 lcas .
semiconductor group 8 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram absolute maximum ratings operating temperature range..............................................................................................0 to 7 0 c storage temperature range.........................................................................................C 55 to 150 c input/output voltage..................................................................................-0.5 to min (vcc+0.5,4.6) v power s upply voltage....................................................................................................-0.5v to 4.6 v power dissipation.............................................................................................................. ........1.3 w data out current (short circuit)............................................................................................... ...50 ma note stresses above those listed under ?absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may effect device reliability. dc characteristics t a = 0 to 70 c, v ss = 0 v, v cc = 3.3 v 0.3 v parameter symbol limit values unit note min. max. input high voltage v ih 2.0 vcc+0.3 v 1) input low voltage v il C 0.3 0.8 v 1) output high voltage (lvttl) output ?h level voltage (iout = -2ma) v oh 2.4 C v output low voltage (lvttl) output ?llevel voltage (iout = +2ma) v ol C 0.4 v output high voltage (lvcmos) output ?h level voltage (iout = -100ua) v oh vcc-0.2 - v ouput low voltage (lvcmos) output ?l level voltage (iout = +100ua) v ol - 0.2 v input leakage current,any input (0 v < vin < vcc , all other pins = 0 v i i(l) C 2 2 m a output leakage current (do is disabled, 0 v < vout < vcc ) i o(l) C 2 2 m a
semiconductor group 9 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram dc-characteristics (contd) t a = 0 to 70 c, v ss = 0 v, v cc = 3.3 v 0.3 v parameter symbol refresh version unit note 2k 4k 8k operating current -40 ns version -50 ns version -60 ns version (ras , cas , address cycling: trc = trc min.) i cc1 250 210 170 155 130 105 110 90 75 ma ma ma 2) 3) 4) standby current (ras =cas =vih) i cc2 222maC ras only refresh current: - -40 ns version -50ns version -60 ns version (ras cycling: cas = vih: trc = trc min.) i cc3 250 210 170 155 130 105 110 90 75 ma ma ma 2) 4) fast page mode current: -40 ns version -50 ns version -60 ns version (ras = v il , cas , address cycling: tpc=tpc min.) i cc4 70 60 50 70 60 50 70 60 50 ma ma ma 2) 3) 4) standby current (ras =cas = vcc-0.2v) i cc5 900 900 900 m aC standby current (l-version) (ras =cas = vcc-0.2v) i cc5 200 200 200 m aC cas before ras refresh current -40 ns version -50 ns version -60 ns version (ras , cas cycling: trc = trc min.) i cc6 250 210 170 155 130 105 155 130 105 ma ma ma 2) 4) self refresh current (l-version only) (cbr cycle with tras>trassmin, cas held low, we = vcc-0.2v, address and din=vcc-0.2v or 0.2v) i cc7 400 400 400 m a
semiconductor group 10 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram ac characteristics (note: 6,7,8) ac64-2f t a = 0 to 70 c, v cc = 3.3 0.3v parameter symbol -40 -50 -60 unit note min. max. min. max. min. max. common parameters random read or write cycle time t rc 75 C 90 C 110 C ns ras pulse width t ras 40 100k 50 100k 60 100k ns cas pulse width t cas 10 100k 13 100k 15 100k ns ras precharge time t rp 25 C 30 C 40 C ns cas precharge time t cp 10 C 10 C 10 C ns row address setup time t asr 0C0C0Cns row address hold time t rah 5C7C10Cns column address setup time t asc 0C0C0Cns column address hold time t cah 5C7C10Cns ras to cas delay time t rcd 15 30 17 37 20 45 ns ras to column address delay t rad 10 20 12 25 15 30 ns ras hold time t rsh 10 C 13 C 15 C ns cas hold time t csh 40 C 50 C 60 C ns cas to ras precharge time t crp 5C5C5Cns transition time (rise and fall) t t 130130130ns 7 refresh period for 8k-refresh t ref C 128 C 128 C 128 ms refresh period for 4k-refresh t ref C64C64C64ms refresh period for 2k-refresh t ref C32C32C64ms refresh period for l-versions t ref C 256 C 256 C 256 ms read cycle access time from ras t rac C40C50C60ns 8, 9 access time from cas t cac C10C13C15ns 8, 9 access time from column address t aa C20C25C30ns 8, 10 oe access time t oea C10C13C15ns 8 column address to ras lead time t ral 20 C 25 C 30 C ns read command setup time t rcs 0C0C0Cns read command hold time t rch 0C0C0Cns 11 read command hold time referenced to ras t rrh 0C0C0Cns 11
semiconductor group 11 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram cas to output in low-z t clz 0C0C0Cns 8 output buffer turn-off delay t off C10C13C15ns 12 output buffer turn-off delay from oe t oez C10C13C15ns 12 data to oe low delay t dzo 0C0C0Cns 13 cas high to data delay t cdd 10 C 13 C 15 C ns 14 oe high to data delay t odd 10 C 13 C 15 C ns 14 write cycle write command hold time t wch 5C7C10Cns write command pulse width t wp 5C7C10Cns write command setup time t wcs 0C0C0Cns 15 write command to ras lead time t rwl 10 C 13 C 15 C ns write command to cas lead time t cwl 10 C 13 C 15 C ns data setup time t ds 0C0C0Cns 16 data hold time t dh 5C7C10Cns 16 cas delay time from din t dzc 0C0C0Cns 13 read-modify -write cycle read-write cycle time t rwc 105 C 126 C 150 C ns ras to we delay time t rwd 55 C 68 C 80 C ns 15 cas to we delay time t cwd 25 C 31 C 35 C ns 15 column address to we delay t ime t awd 35 C 43 C 50 C ns 15 oe command hold time t oeh 5C7C10Cns fast page mode cycle fast page mode cycle time t pc 30 C 35 C 40 C ns access time from cas precharge t cpa C25C30C35ns 8 ras pulse width t ras 40 200k 50 200k 60 200k ns cas precharge to ras delay t rhpc 25 C 30 C 35 C ns ac characteristics (contd) (note: 6,7,8) ac64-2f t a = 0 to 70 c, v cc = 3.3 0.3v parameter symbol -40 -50 -60 unit note min. max. min. max. min. max.
semiconductor group 12 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram fast page mode read-modify -write cycle fast page mode read-write cycle time t pr wc 60 C 71 C 80 C ns cas precharge to we t cpwd 40 C 48 C 55 C ns cas -before-ras refresh cycle cas setup time t csr 5C5C5Cns cas hold time t chr 5C5C10Cns ras to cas precharge time t rpc 0C0C0Cns write to ras precharge time t wrp 5C5C10Cns write hold time referenced to ras t wrh 5C5C10Cns self refresh cycle (l-version only) ras pulse width t rass 100k C 100k C 100k C ns 17 ras precharge time t rps 75 C 90 C 110 C ns 17 cas hold time t chs -50 C -50 C -50 C ns 17 capacitance t a = 0 to 70 c, v cc = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a11,a12) c i1 C5pf input capacitance (ras , cas , we , oe ) c i2 C7pf i/o capacitance (i/o1-i/o8) c io C7pf ac characteristics (contd) (note: 6,7,8) ac64-2f t a = 0 to 70 c, v cc = 3.3 0.3v parameter symbol -40 -50 -60 unit note min. max. min. max. min. max.
semiconductor group 13 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram notes: 1) all voltages are referenced to vss. vih may overshoot to vcc + 2.0 v for pulse widths of < 4ns with 3.3v. vil may undershoot to -2.0v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. 2) icc1, icc3, icc4 and icc6 and icc7 depend on cycle rate. 3) icc1 and icc4 depend on output loading. sp ecified values are measured with the output open. 4) address can be changed once or less while ras = vil.in the case of icc4 it can be changed once or less during a fast page mode cycle ( tpc). 5) an initial pause of 100 m s is required after power-up followed by 8 ras -only-refresh cycles, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 5 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. also, transition times are measured between vih and vil. 8) measured with the specified current load and 100 pf at voh = 2.0 v and vol = 0.8 v. 9) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 10) operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 11) either trch or trrh must be satisfied for a read cycle. 12) toff (max.) and toez (max.) def ine the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) either tdzc or tdzo must be satisfied. 14) either tcdd or todd must be satisfied. 15) twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 16) these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read- modif y-write cycles. 17) when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refresh in an evenly distributed manner over the refresh iterval using cbr refresh cycles, then only one cbr cycle must be performed immediatly after exit from self refresh. if row addresses are being refresh in any other manner (ror - distributed/burst or cbr-burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from self refresh
semiconductor group 14 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram read cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa row column row aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa valid data out ras ucas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z a aaa a aaa a aaa a aaa a aaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l wl1 lcas
semiconductor group 15 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram write cycle (early write) aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa ras ucas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa row row t rah t wcs aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa h or l wl2 lcas
semiconductor group 16 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram write cycle (oe controlled write) aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a valid data aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t rwl t wp t oeh t odd t cwl aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t dzo t oea t clz t ds t oez aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa t dh t rc aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa v ih v il row t dzc aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l hi-z hi-z column row t asc t rad t ral t cah t rah ras ucas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr wl3 lcas
semiconductor group 17 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram read-write (read-modify-write) cycle aaa aaa aaa aaa aaa aaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa row row t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il t asr column t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l t asc v ih v il v ih v il ras ucas address v ih v il wl4 lcas
semiconductor group 18 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram fast page mode read cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaa aaa aaa aaa aaa aaa aaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa t rasp t cas t cas t pc t cp t rcd t csh t cah t cah t asc t asc t asr t rah t rad t rcs t rcs t rcs t asc t cah t cas t rsh t crp t rp t asr t rch t cpa t oea t oea t aa t aa t dzc t dzc t cdd t rrh t cpa t oea t aa t dzc t dzo t odd t odd t dzo t odd t dzo t off t oez t oez t off t oez t cac t cac t clz t clz t clz t off t rac t cac va lid data out data out data out valid valid column column row row ras i/o (outputs) i/o (inputs) oe we address ucas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l t rhcp t rch v oh v ol column fpm1 lcas
semiconductor group 19 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram fast page mode early write cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a t ras t rp t rsh t cas t cas t cp t crp t ral t cah t asr t cwl t rwl t cah t asc t asc t cwl t cwl t wcs t wcs t wcs t wch t wp t wp t wch t wp t wch t rad t cas t rcd t pc t cah t rah t asr t asc t dh t ds t ds t dh t dh t ds column column column row valid data in valid valid data in data in column hi-z ras i/o (outputs) i/o (inputs) oe we address ucas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa h or l v oh v ol fpm2 lcas
semiconductor group 20 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram fast page mode read-modify-write cycle aaaa aaaa aaaa aaaa aa aa aa aa aaaa aaaa aaaa aaaa aa aa aa aa aaaa aaaa aaaa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il ucas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol we oe address i/o (inputs) i/o (outputs) data in data in data in data out out data data out row column address column row t ras t csh column t cpwd t cpwd aaaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aaa aa a aa a aa a aa a aa a aa a aaa h or l t oez lcas
semiconductor group 21 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram ras -only refresh cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row row hi-z address ras ucas i/o (outputs) aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l wl9 lcas
semiconductor group 22 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram cas -before-ras refresh cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l ras i/o (outputs) i/o (inputs) oe we ucas v oh v ol wl10 lcas
semiconductor group 23 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram hidden refresh cycle (read) aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa ras i/o (outputs) i/o (inputs) oe we address ucas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa h or l valid data out row column row hi-z v oh v ol wl11 lcas
semiconductor group 24 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram hidden refresh write cycle aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa ras i/o (output) i/o (input) we address v ih v il v ih v il v ih v il ucas v ih v il v ih v il a aaa a aaa a aaa a aaa a aaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc row row valid data hi-z column v oh v ol t wrp t wrh wl12 lcas
semiconductor group 25 hyb3164(5/6)160at(l)-40/-50/-60 4m x 16-dram cas-before-ras self refresh (?sleep mode) aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z aaaa a aaa a aaa a aaa a aaa a aaa aaaa aaaa aaa a aaa a aaa a aaa a aaa a aaaa h or l ras i/o (outputs) i/o (inputs) oe we ucas v oh v ol t chs wl13 lcas
semi c onduc t or group 2 6 hyb 3 164(5/6)1 6 0 a t ( l ) - 4 0 /-5 0 /-60 4m x 16-d r am packa g e o u tl i nes plast i c pa c kag e p - t sopi i -50 (400 m i l width, 0. 8 mm lead pitch, thin s mall outline, smd)

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